In semiconductor memory devices, receiver circuits are used as an interface between a processor and other components of the semiconductor memory device. Such receiver circuits receive input signals, such as input data signals, and generate output signals, which are processed by further circuit components inside the semiconductor memory device. In most cases the receiver circuits are designed as differential receiver circuits that convert data from a low swing NRZ (non return to zero) voltage to full swing CMOS-levels. As the operating frequencies of processors increase from generation to generation, along with increases in processor bandwidth and the corresponding bandwidth of the data provided to the interface receiver circuit, interface circuits need to adapt to these changed operating conditions.
An issue in the design of input receiver circuits is to provide the output signal of the receiver circuit as a low-jitter signal to meet set-up and hold time requirements for a high-speed sampling process performed by flip-flops. For an input receiver circuit using a single-ended reception of data, one terminal of the input receiver circuit is actuated by an input signal which is to be amplified, and the other terminal is actuated by a reference signal. FIG. 1 shows an input receiver circuit designed as a differential amplifier stage 50 comprising a differential amplifier circuit 50a and a differential amplifier circuit 50b. The differential amplifier circuit 50a is designed as a PMOS input differential amplifier circuit, whereas circuit 50b is designed as an NMOS input differential amplifier circuit.
The PMOS input differential amplifier circuit 50a includes a PMOS transistor 51a, another PMOS transistor 52a, an NMOS transistor 53a, another NMOS transistor 54a, and a current source 55a. The PMOS transistor 51a is connected at its gate to an input terminal E51a for applying an input signal, at its source to the current source 55a, and at its drain to the drain of the NMOS transistor 53a. The NMOS transistor 53a is connected at its drain to the drain of the PMOS transistor 51a, and at its source to a reference voltage VSS. The NMOS transistor 54a is connected at its gate to the gate of the NMOS transistor 53a, at its drain to the gate of the NMOS transistor 53a and the drain of the PMOS transistor 52a, and at its source to the reference voltage VSS. The current source 55a is connected at one of its terminals to a power supply voltage VDD and at its other terminal to the source of the PMOS transistor 51a and the source of the PMOS transistor 52a. It is controlled by a control signal BIASP. An output terminal A50a of the PMOS input differential amplifier circuit 50a is connected to a junction between the drain of the PMOS transistor 51a and the drain of the NMOS transistor 53a and outputs an output signal of the PMOS input differential amplifier circuit 50a. 
The NMOS input differential amplifier circuit 50b includes an NMOS transistor 51b, another NMOS transistor 52b, a PMOS transistor 53b, another PMOS transistor 54b, and a current source 55b. The PMOS transistor 53b is connected at its source to a power supply voltage VDD, and at its drain to the drain of the NMOS transistor 51b. The PMOS transistor 54b is connected at its source to the power supply voltage VDD, and at its drain to the gate of the PMOS transistor 53b and the drain of the NMOS transistor 52b. The NMOS transistor 51b is connected at its gate to an input terminal E51b for applying an input signal IN, at its drain to the drain of the PMOS transistor 53b, and at its source to the current source 55b. The NMOS transistor 52b is connected at its gate to a reference terminal E52b for applying a reference signal REF, at its drain to the drain of the PMOS transistor 54b, and at its source to the current source 55b. The current source 55b is connected at one of its terminals to a reference voltage VSS and at its other terminal to the source of the NMOS transistor 51b and the source of the NMOS transistor 52b. It is controlled by a control signal BIASN. An output terminal A50b of the NMOS input differential amplifier circuit 50b is connected to a junction between the drain of the PMOS transistor 53b and the drain of the NMOS transistor 51b and outputs an output signal of the NMOS differential circuit 50b. 
FIG. 1 shows two differential amplifiers in a parallel configuration. The PMOS input differential amplifier preferably operates for amplifying an input signal IN which is below a level of the reference signal REF. The NMOS input differential amplifier preferably operates for amplifying an input signal, wherein a level of the input signal is above a level of the reference signal REF.
FIG. 2 shows two input signals IN1 and IN2 symmetrically oscillating around a level of a reference signal REF1 or REF2. The level of the reference signal varies between reference level REF1 and REF2, wherein the input signal swing is coupled to the variation of the reference signal. The level of the reference signal REF1 is lower than the level of the reference signal REF2. This variation occurs in a system having a high variation of the power supply voltage from a transmitting device, or if transmitting and receiving devices have different potentials.
FIG. 3 shows an asymmetrical waveform of an input signal IN oscillating around different levels of a reference signal REF. The input signal swing oscillates around a constant level. The reference signal REF varies between a low level REFMIN and a high level REFMAX. Such a level variation of the reference signal occurs especially when the reference signal REF is very noisy due to coupling from neighboring transitioning signals, or when the reference signal is generated by noisy power supplies.
The architecture of the receiver circuit shown in FIG. 1 works correctly only for a supply voltage considerably higher than the reference voltage REF. However, reductions in supply voltages in the latest technologies render this voltage comparable to the reference voltage and hence give rise to variations of the level of the reference signal. Variations in the voltage level of the reference signal increase the signal skew in the system and hence decrease the set-up and hold margin for the data if a sampling clock is having a differential input swing.
Variations in the level of the reference signal as shown in FIGS. 2 and 3 will turn off the PMOS input differential amplifier 50a resulting in signal skew (jitter) and duty cycle distortion. If PMOS input differential amplifier circuit 50a and NMOS input differential amplifier circuit 50b are designed for a low level of a reference signal REF, they produce a duty cycle error such that a low level of an amplified output signal OS is generated with a longer duration than a high level of the amplified output signal, even if the high and low levels of the input signal IN have the same duration. Conversely, if PMOS input differential amplifier circuit 50a and NMOS input differential amplifier circuit 50b are designed for a high level of a reference signal REF, they produce a duty cycle error such that a high level of an amplified output signal OS is generated with a longer duration than a low level of the amplified output signal, even if the high and low levels of the input signal IN have the same duration.
FIG. 4 shows another conventional circuit design. The differential amplifier stage 50 is identical to the circuit stage illustrated in FIG. 1. FIG. 4 additionally contains a control stage 60. The amplifier stage 50 provides amplification, and the control stage 60 reduces an offset current generated by the amplifier stage 50. The offset current may be caused by a transistor mismatch within amplifier stage 50. The control stage 60 comprises a resistor-connected inverter followed by another inverter 64. The resistor-connected inverter comprises a PMOS transistor 61 which is coupled between a power supply voltage VDD and an input E64 of the inverter 64. An NMOS transistor 62 is coupled between a reference voltage VSS and the input E64 of the inverter 64. The control terminals E61 of transistor 61 and E62 of transistor 62 are connected to the output A50 of the differential amplifier stage 50. The resistor 63 is coupled between the output terminal A50 of the amplifier stage 50 and the input E64 of the inverter 64. The control stage 60 generates at an output terminal A60 an output signal OUT with an offset current reduced in comparison to the offset current generated by the amplifier stage 50.
Similar to the control stage 60 of FIG. 4, U.S. Patent Publication No. US 2004/174191 discloses an offset-reducing block cascaded with a differential pre-amplifier and arranged for reducing the offset generated by the differential pre-amplifier, and a buffering block in series with the offset-reducing block and arranged for amplifying and buffering the output voltage of the offset-reducing block.
However, the circuit design shown in FIG. 4 will also provide duty cycle distortion for the output signal OUT if the supply voltage VDD is comparable to the reference voltage REF, as the PMOS input differential amplifier circuit 50a is turned to an off-state.